I. Field of the Disclosure
The technology of the disclosure relates generally to non-volatile memory, and particularly to memory write driver circuits for providing write currents to a memory to perform write operations.
II. Background
Processor-based computer systems include memory for data storage. Memory systems are composed of resistive memory elements capable of storing data, wherein the form of the stored data depends on the type of memory employed. In particular, magnetic random access memory (MRAM) is an example of non-volatile memory in which data is stored by programming a magnetic tunnel junction (MTJ) of an MRAM bitcell. Data is stored in an MTJ as a magnetic state, wherein no electric current is required to preserve a stored data value. Thus, an MTJ can store data even when power is not supplied to the MTJ. Conversely, memory that stores data in the form of an electric charge, such as static random access memory (SRAM), requires power to preserve a stored data value. Thus, because an MTJ may store information even when power is turned off, particular circuits and systems may benefit from employing MRAM.
In this regard, FIG. 1 illustrates an exemplary MRAM bitcell 100 that includes a metal-oxide semiconductor (MOS) (typically n-type MOS, i.e., NMOS) access transistor 102 integrated with an MTJ 104 for storing non-volatile data. The MRAM bitcell 100 may be provided in an MRAM memory used as memory storage for any type of system requiring electronic memory, such as a central processing unit (CPU) or processor-based system, as examples. The MTJ 104 includes a pinned layer 106 and a free layer 108 disposed on either side of a tunnel barrier 110 formed by a thin non-magnetic dielectric layer. When the magnetic orientation of the pinned layer 106 and the free layer 108 are anti-parallel (AP) to each other, a first memory state exists (e.g., a logical ‘1’). When the magnetic orientation of the pinned layer 106 and the free layer 108 are parallel (P) to each other, a second memory state exists (e.g., a logical ‘0’). Further, the access transistor 102 controls reading and writing data to the MTJ 104. A drain (D) of the access transistor 102 is coupled to a bottom electrode 112 of the MTJ 104, which is coupled to the pinned layer 106. A word line 114 is coupled to a gate (G) of the access transistor 102. A source (S) of the access transistor 102 is coupled to a source line 116, which is coupled to a write driver 118. A bit line 120 is coupled to the write driver 118 and a top electrode 122 of the MTJ 104, which is coupled to the free layer 108.
With continuing reference to FIG. 1, when writing data to the MTJ 104, the gate (G) of the access transistor 102 is activated by activating the word line 114, which couples a write current (Iw) from the write driver 118 on the source line 116 to the bottom electrode 112. The write current (Iw) provided by the write driver 118 to the MTJ 104 must be strong enough to change the magnetic orientation of the free layer 108. Particularly, the write current (Iw) must be at least equal to the critical switching current (Ic) to change the magnetic orientation of the free layer 108, wherein the critical switching current (Ic) is the current required to change the magnetic orientation. If the magnetic orientation is to be changed from AP to P, a current flowing from the top electrode 122 to the bottom electrode 112 induces a spin transfer torque (STT) at the free layer 108 that can change the magnetic orientation of the free layer 108 to P with respect to the pinned layer 106. If the magnetic orientation is to be changed from P to AP, a current flowing from the bottom electrode 112 to the top electrode 122 induces an STT at the free layer 108 to change the magnetic orientation of the free layer 108 to AP with respect to the pinned layer 106.
In this regard, because writing to MTJs requires a change in the orientation of a magnetic field, writing to MTJs is inherently probabilistic. More specifically, the critical switching current (Ic) of the MTJ 104 may vary over time. Thus, applying the write current (Iw) to the MTJ 104 during a first write operation may cause the magnetic orientation of the free layer 108 to properly change orientation, resulting in a successful write. Conversely, applying the write current (Iw) to the MTJ 104 during a second write operation may not cause the magnetic orientation of the free layer 108 to properly change orientation, resulting in a write failure. One option to overcome the probabilistic nature of MTJs and reduce the amount of corresponding write failures is to increase the strength of the write current (Iw) to a constant level exceeding the critical switching current (Ic). However, because the MTJ 104 is a resistive memory element with a given resistance level (R(mtj)), applying the write current (Iw) to the MTJ 104 during a write operation generates a voltage (V(mtj)) across the MTJ 104 according to (V(mtj))=(Iw)*(R(mtj)). Further, due to process, voltage, and temperature (PVT) variations related to MTJ fabrication, multiple MTJs of the same design and fabrication process may have varying resistance levels (R(mtj)). Applying a write current (Iw) whose strength exceeds the level of the critical switching current (Ic) could cause certain MTJs with higher resistances (R(mtj)) to breakdown as a result of generating a breakdown voltage (V(bd)), while other MTJs of the same design with lower resistances (R(mtj)) would not breakdown. Thus, although increasing the strength of the write current (Iw) to a constant level exceeding the critical switching current (Ic) may avoid write failures due to the probabilistic nature of MTJs, doing so may increase write failures attributable to breakdown, making it difficult to achieve a target write error rate (WER) yield.
Therefore, it would be advantageous to provide a write current (Iw) to MTJs in an MRAM that is strong enough to successfully perform write operations, while remaining low enough to reduce write errors associated with breakdown voltage (V(bd)) so as to achieve a target WER yield.